Description
This program attaches interrupt with different mode for Intel Ethernet Controller I225/I226.
The different interrupt mode is programmed into device's General-Purpose Interrupt Enable register (GPIE) and calls appropriate RtAttachInterrupt version. In MSIX_MULTIVECTOR mode, it generates multiple interrupts by setting extended interrupt cause register. The interrupts are evenly distributed within the affinity mask of the calling process. The program checks the calling counts of interrupt handling routines run by MIST to ensure no interrupt loss. The program also measures the latency from interrupt events setting to MIST handling.
Note: This test takes control of the Network Interface Card (NIC) independent of the TCP/IP Stack. To run correctly, the TCP/IP Stack should not use the NIC (i.e., it should be disabled if it is in the list of interfaces managed by the TCP/IP Stack). If the TCP/IP Stack is using the NIC when this test is run, you will see the following error: WARNING: Attach multiple vector interrupts failed, error 1119
Source Files
| File | Description |
|---|---|
|
MultiIntrModeI225.c |
Usage
MultiIntrModeI225.ertos <Number of Queues> <Fire Interrupts Together> <Loop Count> <Interrupt Mode>
Number of Queues: Integer specifying how many receive/ transmit queue pairs per port to test (0-4). The default value is 0 (auto – allows the program to decide based on free vectors and messages).
Fire Interrupts Together: Integer specifying how to fire multiple interrupts. 0 – fire separate, 1 – fire together. The default value is 0.
Loop Count: Integer specifying the number of times the loop will be performed. The default value is 10000.
Interrupt Mode: Integer specifying the different interrupt mode to program into the device register. 1 – MSI extended, 2 – MSIX single vector, 3 – MSIX multi vector. The default value is 3.
Examples
This example is for an I226 card using two queue pairs with different interrupt modes. In this scenario, we use the following command line syntax separately for each interrupt mode:
run /t 1 MultiIntrModeI225 2 0 10000 1
Output
MultiIntrModeI225 test started Number of Queues: 2, Loop Count: 10000, Interrupt Mode: MSI_EXTEND Found an I225 at location 3;0;0 ! PciCommand: 0x100, PciStatus: 0x10 Reset and read back PciCommand: 0x106, PciStatus: 0x10 The device/function has both MSI and MSIX capabilities MSI MessageControl: 0x181 MsgAddr 0xfee00000, MsgUpperAddr 0x0, MsgData 0x40ee MaskBits 0x0, PendingBits 0x0 RegCtrl: 0x81c0641, RegStatus: 0x680680 MultiIntrModeI225 test: PASS! Total Attempts: 10000, Total interrupts: 10000 Vector #0, Core # 0, IST Latency: Maximum 9 (us), Average 5 (us)
run /t 1 MultiIntrModeI225 2 0 10000 2
Output
MultiIntrModeI225 test started Number of Queues: 2, Loop Count: 10000, Interrupt Mode: MSIX_SINGLEVECTOR Found an I225 at location 3;0;0 ! PciCommand: 0x106, PciStatus: 0x10 Reset and read back PciCommand: 0x106, PciStatus: 0x10 The device/function has both MSI and MSIX capabilities MSIX MessageControl: 0x8004 MsixTablePhysAddr: 0xd1200000, PciMsixTableAddr: 0xd1200000 msgId 0, MsgAddr 0xfee00000, MsgUpperAddr 0x0, MsgData 0x40ee, VectorCtrl 0x0 PciMsixPBA: 0xd1202000, PciMsixPBAddr: 0xd1202000, *PciMsixPBAddr: 0x0 RegCtrl: 0x81c0641, RegStatus: 0x680680 MultiIntrModeI225 test: PASS! Total Attempts: 10000, Total interrupts: 10000 Vector #0, Core # 0, IST Latency: Maximum 7 (us), Average 4 (us)
run /t 1 MultiIntrModeI225 2 0 10000 3
Output
MultiIntrModeI225 test started
Number of Queues: 2, Fire Interrupts Together: 0, Loop Count: 10000, Interrupt Mode: MSIX_MULTIVECTOR
Found an I225 at location 3;0;0 ! PciCommand: 0x106, PciStatus: 0x10
Reset and read back PciCommand: 0x106, PciStatus: 0x10
The device/function has both MSI and MSIX capabilities
MSIX MessageControl: 0x8004
MsixTablePhysAddr: 0xd1200000, PciMsixTableAddr: 0xd1200000
msgId 0, MsgAddr 0xfee00000, MsgUpperAddr 0x0, MsgData 0x40ee, VectorCtrl 0x0
msgId 1, MsgAddr 0xfee02000, MsgUpperAddr 0x0, MsgData 0x40ee, VectorCtrl 0x0
msgId 2, MsgAddr 0xfee04000, MsgUpperAddr 0x0, MsgData 0x40ee, VectorCtrl 0x0
msgId 3, MsgAddr 0xfee06000, MsgUpperAddr 0x0, MsgData 0x40ee, VectorCtrl 0x0
msgId 4, MsgAddr 0xfee08000, MsgUpperAddr 0x0, MsgData 0x40ee, VectorCtrl 0x0
PciMsixPBA: 0xd1202000, PciMsixPBAddr: 0xd1202000, *PciMsixPBAddr: 0x0
RegCtrl: 0x81c0641, RegStatus: 0x680680
MultiIntrModeI225 test: PASS!
Vector #0, Core # 0, IST Latency: Maximum 7 (us), Average 2 (us)
Vector #1, Core # 1, IST Latency: Maximum 5 (us), Average 2 (us)
Vector #2, Core # 2, IST Latency: Maximum 6 (us), Average 2 (us)
Vector #3, Core # 3, IST Latency: Maximum 5 (us), Average 2 (us)
Vector #4, Core # 4, IST Latency: Maximum 6 (us), Average 2 (us)
run /t 1 MultiIntrModeI225 2 1 10000 3
Output
MultiIntrModeI225 test started Number of Queues: 2, Fire Interrupts Together: 1, Loop Count: 10000, Interrupt Mode: MSIX_MULTIVECTOR Found an I225 at location 3;0;0 ! PciCommand: 0x106, PciStatus: 0x18 Reset and read back PciCommand: 0x106, PciStatus: 0x18 The device/function has both MSI and MSIX capabilities MSIX MessageControl: 0x8004 MsixTablePhysAddr: 0xd1200000, PciMsixTableAddr: 0xd1200000 msgId 0, MsgAddr 0xfee00000, MsgUpperAddr 0x0, MsgData 0x40ee, VectorCtrl 0x0 msgId 1, MsgAddr 0xfee02000, MsgUpperAddr 0x0, MsgData 0x40ee, VectorCtrl 0x0 msgId 2, MsgAddr 0xfee04000, MsgUpperAddr 0x0, MsgData 0x40ee, VectorCtrl 0x0 msgId 3, MsgAddr 0xfee06000, MsgUpperAddr 0x0, MsgData 0x40ee, VectorCtrl 0x0 msgId 4, MsgAddr 0xfee08000, MsgUpperAddr 0x0, MsgData 0x40ee, VectorCtrl 0x0 PciMsixPBA: 0xd1202000, PciMsixPBAddr: 0xd1202000, *PciMsixPBAddr: 0x0 RegCtrl: 0x81c0641, RegStatus: 0x680680 MultiIntrModeI225 test: PASS! Vector #0, Core # 0, IST Latency: Maximum 7 (us), Average 4 (us) Vector #1, Core # 1, IST Latency: Maximum 7 (us), Average 4 (us) Vector #2, Core # 2, IST Latency: Maximum 8 (us), Average 4 (us) Vector #3, Core # 3, IST Latency: Maximum 7 (us), Average 5 (us) Vector #4, Core # 4, IST Latency: Maximum 8 (us), Average 4 (us)
Vector #: The MSI-X vector number through which the interrupts pass the PCIe bus.
Core #: The processor/core number to which the interrupt is targeted.
IST Latency: The latency (in micro-seconds) from interrupt event setting by main thread to its IST handling. This latency includes hardware (MMIO read/write, PCIe, MSI-X, etc.) latency and software (ISR, IST) latency. Maximum is the maximum latency value among the number of loops. Average is the averaged latency values among the number of loops.
