Intel® Raptor Lake (13th/14th Gen) and Alder Lake (12th Gen) provide a performance hybrid architecture combining Performance-cores (P-cores) and Efficient-cores (E-cores). UEFI BIOS orders the active cores on the system from P-cores to E-cores; i.e., if you have 4 P-cores and 4 E-cores, the processor numbers assigned to P-cores will be 0, 1, 2, 3 and the E-cores will be 4, 5, 6, 7. To optimize eRTOS performance on a hybrid architecture, run the ProcessorHybridInfo utility before you design eRTOS applications. You may need to assign (affine) P-cores to those processes/threads with high priority and requiring intensive computing. Assign (affine) E-cores to those processes/threads with low priority and executing background tasks.
Raptor Lake and Alder Lake also provide a new hardware feature called Thread Director, which monitors thread run time instructions to determine a thread’s workload, which is then assigned a class. Thread Director uses its energy and performance core scoring logic to help determine the optimal cores on which to run a given thread.
The ProcessorHybridInfo utility displays each core type, performance capability, and thread class ID for different sets of assembly instructions. You can use this information when deciding which cores to run threads on.
Note: When executing a critical section, E-cores may reduce the speed of P-cores. Some UEFI/BIOS may have the option to disable E-cores.
| Instruction set | Class ID |
|---|---|
|
Default |
0 |
|
Integer Registers |
1 |
|
AVX/AVX2 |
2 |
|
Pause |
3 |
Running the Utility
Note: Run ProcessorHybridInfo after the system boots with eRTOS.
In the Command Prompt on eRTOS Console, type: Run ProcessorHybridInfo.ertos
Output
|
Output |
Meaning |
|---|---|
|
The processor is a hybrid part |
The processor is Intel® Raptor Lake (13th/14th Gen) or Alder Lake (12th Gen). |
|
Intel Thread Director (ITD) is supported |
The processor has Thread Director capability. |
|
Intel Thread Director (ITD) is enabled at package scope |
The Thread Director is enabled at package scope by eRTOS. |
|
Number of classes in hardware feedback structure |
The number of thread characteristic classes in each capability. |
|
Number of capabilities in hardware feedback structure |
The number of available capabilities (usually 2). |
|
HRESET Enabled |
Allows history to be reset upon thread switching. |
|
ProcIndex |
The index in the hardware feed structure for the specified core. |
|
The processor is not a hybrid part |
The system is not a performance hybrid architecture. |
Example
C:\>run D:\ProcessorHybridInfo The processor is a hybrid part. Intel Thread Director (ITD) is supported. Intel Thread Director (ITD) is enabled at package scope. Number of classes in hardware feedback structure: 4 Number of capabilities in hardware feedback structure: 2 ------------------------------------ Performance cores and Efficiency cores layout. ITD, HRESET, Processor index Core- 0: P_Core, ITD Enabled, HRESET Enabled, ProcIndex 0 Core- 1: P_Core, ITD Enabled, HRESET Enabled, ProcIndex 1 Core- 2: P_Core, ITD Enabled, HRESET Enabled, ProcIndex 2 Core- 3: P_Core, ITD Enabled, HRESET Enabled, ProcIndex 3 Core- 4: P_Core, ITD Enabled, HRESET Enabled, ProcIndex 4 Core- 5: P_Core, ITD Enabled, HRESET Enabled, ProcIndex 5 Core- 6: P_Core, ITD Enabled, HRESET Enabled, ProcIndex 6 Core- 7: P_Core, ITD Enabled, HRESET Enabled, ProcIndex 7 Core- 8: E_Core, ITD Enabled, HRESET Enabled, ProcIndex 9 Core- 9: E_Core, ITD Enabled, HRESET Enabled, ProcIndex 9 Core-10: E_Core, ITD Enabled, HRESET Enabled, ProcIndex 9 Core-11: E_Core, ITD Enabled, HRESET Enabled, ProcIndex 9 ------------------------------------ Performance Capability (0 ... 255), higher values indicate higher performance Core- 0: Class 0: 0x3d, Class 1: 0x48, Class 2: 0x60, Class 3: 0x30 Core- 1: Class 0: 0x3d, Class 1: 0x48, Class 2: 0x60, Class 3: 0x30 Core- 2: Class 0: 0x3d, Class 1: 0x48, Class 2: 0x60, Class 3: 0x30 Core- 3: Class 0: 0x3d, Class 1: 0x48, Class 2: 0x60, Class 3: 0x30 Core- 4: Class 0: 0x3f, Class 1: 0x4a, Class 2: 0x62, Class 3: 0x31 Core- 5: Class 0: 0x3d, Class 1: 0x48, Class 2: 0x60, Class 3: 0x30 Core- 6: Class 0: 0x3f, Class 1: 0x4a, Class 2: 0x62, Class 3: 0x31 Core- 7: Class 0: 0x3d, Class 1: 0x48, Class 2: 0x60, Class 3: 0x30 Core- 8: Class 0: 0x24, Class 1: 0x24, Class 2: 0x24, Class 3: 0x24 Core- 9: Class 0: 0x24, Class 1: 0x24, Class 2: 0x24, Class 3: 0x24 Core-10: Class 0: 0x24, Class 1: 0x24, Class 2: 0x24, Class 3: 0x24 Core-11: Class 0: 0x24, Class 1: 0x24, Class 2: 0x24, Class 3: 0x24 ------------------------------------ Thread class ID and ideal core for each type of ISA instructions running on each core Core- 0: INTEGER: 1, Ideal-Core: 4, AVX2: 2, Ideal-Core: 4, PAUSE: 3, Ideal-Core: 4 Core- 1: INTEGER: 1, Ideal-Core: 4, AVX2: 2, Ideal-Core: 4, PAUSE: 3, Ideal-Core: 4 Core- 2: INTEGER: 1, Ideal-Core: 4, AVX2: 2, Ideal-Core: 4, PAUSE: 3, Ideal-Core: 4 Core- 3: INTEGER: 1, Ideal-Core: 4, AVX2: 2, Ideal-Core: 4, PAUSE: 3, Ideal-Core: 4 Core- 4: INTEGER: 1, Ideal-Core: 4, AVX2: 2, Ideal-Core: 4, PAUSE: 3, Ideal-Core: 4 Core- 5: INTEGER: 1, Ideal-Core: 4, AVX2: 2, Ideal-Core: 4, PAUSE: 3, Ideal-Core: 4 Core- 6: INTEGER: 1, Ideal-Core: 6, AVX2: 2, Ideal-Core: 6, PAUSE: 3, Ideal-Core: 6 Core- 7: INTEGER: 1, Ideal-Core: 4, AVX2: 2, Ideal-Core: 4, PAUSE: 3, Ideal-Core: 4 Core- 8: INTEGER: 0, Ideal-Core: 4, AVX2: 0, Ideal-Core: 4, PAUSE: 0, Ideal-Core: 4 Core- 9: INTEGER: 0, Ideal-Core: 4, AVX2: 0, Ideal-Core: 4, PAUSE: 0, Ideal-Core: 4 Core-10: INTEGER: 0, Ideal-Core: 4, AVX2: 0, Ideal-Core: 4, PAUSE: 0, Ideal-Core: 4 Core-11: INTEGER: 0, Ideal-Core: 4, AVX2: 0, Ideal-Core: 4, PAUSE: 0, Ideal-Core: 4
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